Girish B. Ratanpal, MSEE, JD, PhD

Senior Associate

J.D., Suffolk University Law School
Ph.D., Electrical Engineering – University of Virginia
M.S., Electrical Engineering – State University of New York at Binghamton
B.E., Industrial Electronics – Pune University

Massachusetts, Court of Appeals of Massachusetts, Massachusetts Supreme Judicial Court

Certifications and Registrations 


Prior to joining the Innovators team in January 2021, Girish spent over fourteen years working as a technical specialist at law firms in Houston and Boston. He is experienced in preparing and prosecuting patent applications in the fields of computer networking, optical networks, Fiber-Channel networks and switches, electronic design automation (EDA), hybrid power supplies, vehicle battery systems, display devices, micro-electro-mechanical (MEMS) devices, optical devices, communication, deep learning, signal processing, analog and digital circuits, medical devices, and consumer electronics, including but not limited to storage area networks, audio and video conferencing systems, and implantable cochlear and spinal stimulators. He has also assisted in patent infringement and invalidity analysis related to complex technologies in the fields of computer networks, encryption, memory systems, display devices, heat exchange controllers, oil field exploration, and power conversion electronics, as well as re-examinations, patent portfolio analysis, and freedom to operate analysis.

Girish’s practice is served by his extensive education in electrical engineering: in addition to his JD from Suffolk University Law School, he holds a PhD in electrical engineering from the University of Virginia, a MS in electrical engineering from the State University of New York at Binghamton, and a Bachelor of Engineering in industrial electronics from Pune University in India. Girish focused his doctoral research in VLSI circuits related to differential power analysis, working as both a research assistant as well as teaching assistant for a senior level course in computer organization and design.

Girish has authored three technical publications, including publications in IEEE Transactions on Secure and Dependable Computing and IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. In addition to his publication list, he has presented at the Great Lakes Symposium on VSLI.

Seasoned in working with both university and corporate clients, Girish has also worked with startups including actively participating in the MassChallenge accelerator program in Boston.

He is based in Boston.

Senior Associate (retained) – Anzu Partners
Technical Specialist – Foley & Lardner LLP
Technical Specialist – Wong Cabello LLP
Technical Specialist – Osha Liang LLP
Research Assistant – University of Virginia
Teaching Assistant – University of Virginia
Research Assistant – State University of New York, Binghamton

Memberships and Affiliations
Institute for Electronics and Electrical Engineers (IEEE)

Dissertations and Theses
PhD Dissertation: Signal Suppression Model of, and An On-chip Countermeasure to, Power Analysis Attacks
MS Thesis: A VLSI 4×4 Crossbar Switch Wrapped Wave Front Arbitration
Undergraduate Project: Electrically Erasable Programmable Read-Only Memory (EEPROM) Programmer


  • “An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks,” G.B. Ratanpal, R.D. Williams, and T.N. Blalock, IEEE Transactions on Secure and Dependable Computing 1(3), 179-189 (2004).
  •  “A VLSI Crossbar Switch with Wrapped Wave Front Arbitration,” J.G. Delgado-Frias and G.B. Ratanpal, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 50(1), 135-41 (2003).
  • “A VLSI Wrapped Wave Front Arbiter for Crossbar Switches,” J.G. Delgado-Frias and G.B. Ratanpal, Proceedings of the 11th Great Lakes Symposium on VLSI, West Lafayette IN, 85-88 (2001)